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RM0008
Advanced-control timers (TIM1&TIM8)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 60. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
05
04 03 02 01 00 36 35 34 33 32 31 30 2F
Counter underflow (cnt_udf)
Update event (UEV)
Update interrupt flag (UIF)
Figure 61. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0002
0001 0000
0036
0035
0034
0033
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 62. Counter timing diagram, internal clock divided by 4
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0001
0000
0036
0035
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Doc ID 13902 Rev 9
261/995
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